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1/17 september 2013 introduction this application note provides with software guidelines and examples for programming st10f269 and st10f280. more generally, this application note is applicable for any st10 variant with 0.35 m m technology embedded flash memory. the first chapter gives an overview the st10f269/f280 embedded flash key features. it also shows the differences between st10f269/st10f280 and st10f168. the second chapter describes how to develop software for st10s embedded flash through guidelines, examples and tips. the last chapter is dedicated to embedded application aspects. more specifically, it gives advises for flash field reprogramming. this application note does not replace st10 product datasheets. it refers to them and it is necessary to have a copy the specific st10 variant targetted by the user to follow some of the explanations. AN1496 application note flash programming / reprogramming st10f269 / st10f280 by andr roger
AN1496 - application note 2/17 1 introduction to st10 0.35mm embedded flash ......................................... 3 1.1 differences with st10f168 ............................................................................... 3 1.1.1 single supply............................................................................................................. .. 3 1.1.2 new erase/program controller.................................................................................... 3 1.1.3 improved granularity of block sizes ........................................................................... 3 1.2 comparison with stand-alone flash memories ...................................... 3 1.2.1 similar but different erase/program commands ........................................................ 3 1.2.2 description of the commands to the flash controller................................................. 3 1.2.3 same flash status register........................................................................................ 5 1.2.4 boot blocks architecture ............................................................................................. 6 1.2.5 protection ................................................................................................................ .... 6 2 writing code for the flash of st10 with 0.35mm embedded flash.. 7 2.1 st10 programming constraints .................................................................... 7 2.2 polling the flash erase program controller ..................................... 7 2.2.1 ready/busy signal ...................................................................................................... 7 2.2.2 flash status register .................................................................................................. 7 2.3 flash memory mapping in st10 space........................................................... 7 2.4 programming command..................................................................................... 8 2.5 erasing command ................................................................................................ 9 2.6 flash protection commands .......................................................................... 10 2.6.1 block protection.......................................................................................................... . 10 2.6.2 code protection........................................................................................................... 10 2.6.2.1 using code protection with st10................................................................................ 10 2.6.2.2 code protection and bootstrap loader ....................................................................... 10 2.6.2.3 code protection and block0 protection....................................................................... 11 2.7 other flash commands ..................................................................................... 12 2.8 tips to reduce flash program and erase times .................................... 12 2.8.1 reducing the programming time................................................................................ 12 2.8.2 reducing erase times ................................................................................................ 12 3 embedded application aspects..................................................................... 13 3.1 reading the flash while erasing or programming .............................. 13 3.1.1 minimum software to be copied into the on-chip ram .............................................. 13 3.1.2 maximizing programming performance at system level ............................................ 13 3.1.3 suspend and resume commands.............................................................................. 13 3.2 field reprogramming with st10f269 ............................................................ 14 3.2.1 reset ..................................................................................................................... ...... 14 3.2.2 list of events and suggested handling methods ........................................................ 14 3.2.2.1 supply out of st specification..................................................................................... 14 3.2.2.2 st10 pll unlock......................................................................................................... 14 3.2.3 generic aspects of flash field reprogramming......................................................... 14 3.2.3.1 completion of the reprogramming process................................................................ 15 3.2.3.2 events that may interrupt the reprogramming process ............................................ 15 4 quick summary ..................................................................................................... 17 5 conclusion ............................................................................................................ 16 6 application note version information...................................................... 16 6.1 revision of 26th of february 2002 ................................................................ 16 table of contents pag e
AN1496 - application note 3/17 1 - introduction to st10 0.35 m m embedded flash this chapter is describing the improvements made from the st10f168 and the differences with stand-alone flash memories. 1.1 - differences with st10f168 1.1.1 - single supply st10 variants with 0.35 m m embedded flash do not require specific programming supply. on-chip charge pumps will provide with the necessary programming supply from the external single 5 volt supply. 1.1.2 - new erase/program controller the 0.35 m m erase/program controller has been changed to be closer to the one of stand-alone flash memories : erasing and programming of flash memory cells is no more done by the st10. this allows : C savings on system stack : there is no more need to allocate space on the st10 system stack for eras- ing and programming, C improved efficiency during programming : st10 cpu can be used to handle communication during the time where the erase/program controller is dealing with the flash, C improved clock scheme : the flash erase/program controller has its own clock; there is no more need to specify it the cpu clock. this also simplifies the handling of special events (like pll unlock) during erasing/programming. 1.1.3 - improved granularity of block sizes st10 0.35 m m embedded flash has improved block granulaty (smaller blocks) and also features boot block organisation : C block size is 64 kbyte for standard blocks, C small blocks for the 4 boot blocks (16 kbyte, then 8 kbyte, 8 kbyte, 32 kbyte). 1.2 - comparison with stand-alone flash memories 1.2.1 - similar but different erase/program commands the erase/program controller of st10f269/f280 is derived from the common flash memory interface : C to keep the same level of proven safety, the special sequence of commands of stand alone flash mem- ories has been kept, C to differentiate from external flash memories, the value of the commands (address and data) have been slighlty modified. this allows to re-use existing software written for stand-alone flash memories with few modifications. the following chapters describe them. 1.2.2 - description of the commands to the flash controller the following table is describing the possible commands with st10f269/f280 erase/program controller. commands to the flash are defined by a sequence of st10 write cycles with specific addresses and data within the flash memory range. the length of the sequence varies from 1 cycle (ex : read/reset) to 6 cycles (chip erase). block erase command can be extended by 1 cycle per additional block to erase. this translates in a maximum of 12 cycles for st10f269 and of 16 cycles for st10f280.
AN1496 - application note 4/17 table 1 : commands for st10 with 0.35 m m embedded flash notes 1. address bit a14, a15 and above are dont care for coded address inputs. 2. x = dont care. 3. wa = write address: address of memory location to be programmed. 4. wd = write data: 16-bit data to be programmed 5. optional, additional blocks addresses must be entered within a time-out delay (96 s) after last write entry, timeout status can be verified through fsb.3 value. when full command is entered, read data polling or toggle bit until erase is completed or suspend ed. 6. read data polling or toggle bit until erase completes. 7. wpr = write protection register. to protect code, bit 15 of wpr must be 0. to protect block n (n=0,1,...), bit n of wpr mu st be 0. bit that are already at 0 in protection register must also be 0 in wpr, else a writing error will occurs (it is not po ssible to write a 1 in a bit already programmed at 0). 8. mem = any address inside the flash memory space. absolute addressing mode must be used (mov mem, rn), and instruction must be executed from flash memory space. 9. odd word address = 4n-2 where n = 0, 1, 2, 3..., ex. 0002h, 0006h... instruction mne cycle 1 st cycle 2 nd cycle 3 rd cycle 4 th cycle 5 th cycle 6 th cycle 7 th cycle read/reset rd 1+ addr. 1 x 2 read memory array until a new write cycle is initiated data xxf0h read/reset rd 3+ addr. 1 x1554h x2aa8h xxxxxh read memory array until a new write cycle is initiated data xxa8h xx54h xxf0h program word pw 4 addr. 1 x1554h x2aa8h x1554h wa 3 read data polling or toggle bit until program completes. data xxa8h xx54h xxa0h wd 4 block erase be 6 addr. 1 x1554h x2aa8h x1554h x1554h x2aa8h ba ba 5 data xxa8h xx54h xx80h xxa8h xx54h xx30h xx30h chip erase ce 6 addr. 1 x1554h x2aa8h x1554h x1554h x2aa8h x1554h note 6 data xxa8h xx54h xx80h xxa8h xx54h xx10h erase suspend es 1 addr. 1 x 2 read until toggle stops, then read or program all data needed from block(s) not being erased then resume erase. data xxb0h erase resume er 1 addr. 1 x 2 read data polling or toggle bit until erase completes or erase is supended another time. data xx30h set block/code protection sp 4 addr. 1 x2a54h x15a8h x2a54h any odd word address 9 data xxa8h xx54h xxc0h wpr 7 read protection status rp 4 addr. 1 x2a54h x15a8h x2a54h any odd word address 9 read protection register until a new write cycle is initiated. data xxa8h xx54h xx90h read pr block temporary unprotection btu 4 addr. 1 x2a54h x15a8h x2a54h x 2 data xxa8h xx54h xxc1h xxf0h code temporary unprotection ctu 1 addr. 1 mem 8 write cycles must be executed from flash. data ffffh code temporary protection ctp 1 addr. 1 mem 8 write cycles must be executed from flash. data fffbh
AN1496 - application note 5/17 1.2.3 - same flash status register the flash status register is used to flag the status of the flash memory and the result of an operation. to maximise the re-use of flash programming software, the flash status register of stand-alone flash memories has been kept. this register can be accessed by read cycles during the program-erase controller operations. the erase/program operation can be controlled by data polling on bit fsb7 of status register, detection of toggle on fsb6 and fsb2, or error on fsb5 and erase timeout on fsb3 bits. any read attempt in flash during erase/program. operation will automatically output these five bits. the e.p.c. sets bits fsb2, fsb3, fsb5, fsb6 and fsb7. other bits are reserved for future use and should be masked. flash status (see note for address) note : the address of the flash status register is the address of the word being programmed when programming operation is in progress, or an address within the block being erased when erasing operation is in progress. 1514131211109876543210 fsb.7 fsb.6 fsb.5 fsb.3 fsb.2 rrr rr bit function fsb.7 flash status bit 7: data polling bit programming operation: this bit outputs the complement of the bit 7 of the word being programmed, and after completion, will output the bit 7 of the word programmed. erasing operation: outputs a 0 during erasing, and 1 after erasing completion. if the block selected for erasure is (are) protected, fsb.7 will be set to 0 for about 100 s, and then return to the previous addressed memory data value. fsb.7 will also flag the erase suspend mode by switching from 0 to 1 at the start of the erase suspend. during program operation in erase suspend mode, fsb.7 will have the same behaviour as in normal pro- gram execution outside the suspend mode. fsb.6 flash status bit 6: toggle bit programming or erasing operations: successive read operations of flash status register will deliver comple- mentary values. fsb.6 will toggle each time the flash status register is read. the program operation is completed when two successive reads yield the same value. the next read will output the bit last pro- grammed, or a 1 after erase operation fsb.6 will be set to1 if a read operation is attempted on an erase suspended block. in addition, an erase suspend/resume command will cause fsb.6 to toggle. fsb.5 flash status bit 5: error bit this bit is set to 1 when there is a failure of program, block or chip erase operations.this bit will also be set if a user tries to program a bit to 1 to a flash location that is currently programmed with 0. the error bit resets after read/reset instruction. in case of success, the error bit will be set to 0 during program or erase and then will output the bit last pro- grammed or a 1 after erasing fsb.3 flash status bit 3: erase time-out bit this bit is set to 1 by the p/e.c. when the last block erase command has been entered to the command interface and it is awaiting the erase start. when the time-out period is finished, after 96 s, fsb.3 returns back to 1. fsb.2 flash status bit 2: toggle bit this toggle bit, together with fsb.6, can be used to determine the chip status during the erase mode or erase suspend mode. it can be used also to identifiey the block being erased suspended. a read operation will cause fsb.2 to toggle during the erase mode. if the flash is in erase suspend mode, a read operation from the erase suspended block or a program operation into the erase suspended block will cause fsb.2 to toggle. when the flash is in program mode during erase suspend, fsb.2 will be read as 1 if address used is the address of the word being programmed. after erase completion with an error status, fsb.2 will toggle when reading the faulty sector.
AN1496 - application note 6/17 1.2.4 - boot blocks architecture st10 with 0.35 m m embedded flash has the same boot blocks as the m29f400 stand-alone flash : 4 boot blocks (16 kbyte, then 8 kbyte, 8 kbyte and 32 kbyte). 1.2.5 - protection compared to stand-alone flash memories, st10 with embedded flash provides with 2 different protections : C block protection, as already implemented on st stand-alone flash memories, protects each block against inadvertent erasing, C code protection, is a set of new commands to protect the proprietary code written in the flash : code protection disables data operands accesses and program branches from any location outside the em- bedded flash. the different protections are controlled through the flash protection register. it is identical of the one of stand-alone flash memories except for the code protection. the flash protection register is a non-volatile register that contains the protection status. this register can be read by using the read protection status (rps) command, and programmed by using the dedicated set protection command. flash protection register (pr) note : the organisation of the flash control register depends on the organisation of each device. please, refer to the targetted product datasheet (ex : st10f269 : bp10, bp9, bp8, bp7 are not implemented). 1514131211109876543210 cp bp10 bp9 bp8 bp7 bp6 bp5 bp4 bp3.3 bp2.2 bp1 bp0 bit function bpx block x protection bit (x = 0...10) 0: the block protection is enabled for block x. programming or erasing the block is not possible, unless a block temporary unprotection command is issued. 1: the block protection is disabled for block x. bit is 1 by default, and can be programmed permanently to 0 using the set protection command but then can not be set to 1 again. it is therefore possible to temporally disable the block protection using the block temporary unprotection instruction. cp code protection bit 0: the flash code protection is enabled.read accesses to the flash for execution not performed in the flash itself are not allowed, the returned value will be 009bh, whatever the content of the flash is. 1: the flash code protection is disabled: read accesses to the flash from external or internal ram are allowed bit is 1 by default, and can be programmed permanently to 0 using the set protection command but then can not be set to 1 again. it is therefore possible to temporally disable the code protection using the code temporary unprotection instruction.
AN1496 - application note 7/17 2 - writing code for the flash of st10 with 0.35 m m embedded flash 2.1 - st10 programming constraints programming language: direct addressing is not allowed for command sequences. all addresses of command cycles shall be defined only with register-indirect addressing mode. as the compiler may generate indirect addressing, the part of the software that generates the commands to the flash should be written in assembly. still part of the software that is not generating the commands can be in higher level language (ex : c). indirect addressing : for command instructions, address bit a14, a15, a16 and a17 are dont care, provided the generated address falls within the flash memory space. this allows to simplify the use of dpp registers when generating commands to the flash : any dpp already pointing to data in the flash memory space can be used to write commands to the flash. C tip : it is also possible to use the extended segment or extended page instructions for addressing the flash. 2.2 - polling the flash erase program controller as soon as the erase program controller (epc) receives the last command of a command sequence, it starts execution of the command. during command execution, the epc status is indicated by 2 sources : C the flash status register, C the read/bust signal. the flash automatically resumes the read mode after the completion of the command. 2.2.1 - ready/busy signal the ready/busy (r /b) signal is connected to the xper2 interrupt node (xp2ic). when r is high, the flash is busy with a program or erase operation and will not accept any additional program or erase instruction. when r /b is low, the flash is ready for any read/write or erase operation. the r /b will also be low when the memory is put in erase suspend mode. this signal can be polled by reading xp2ic register, or can be used to trigger an interrupt when the flash goes from busy to ready. this feature may not be available for all st10 variants in 0.35 m m technology (ex : not available for st10f280). please, check the product datasheet. 2.2.2 - flash status register the flash status register has been described in the previous chapter. this method of polling st10 embedded flash is the one recommanded : the method will be implemented on all st10 variants in 0.35 m m technology. 2.3 - flash memory mapping in st10 space as defined for all st10 derivatives, the lower 32 kbyte part of the embedded flash memory can be mapped into 2 different segments. the flash mapping is controlled by bit roms1 in register syscon. note : the memory mapping of the other block is independant of bit roms1. table 2 : flash memory block mapping block addresses (segment 0) addresses (segment 1) size (bytes) 0 1 2 000000h to 003fffh 004000h to 005fffh 006000h to 007fffh 010000h to 013fffh 014000h to 015fffh 016000h to 017fffh 16 k 8 k 8 k
AN1496 - application note 8/17 2.4 - programming command in the examples hereafter, the 16-bit registers r11 and r12 are used as auxilary registers for indirect addressing. the following examples use dpp0. we just to have to make sure that dpp0 points to the active flash area. to be independant of the mapping of sector 0, we choose here segment2 for dpp (i.e. : dpp0 = 08h). example : performing a program word command we assume that in the initialization phase the lowest 32 kbyte of flash memory (sector 0) have been mapped to segment 1. the data to be written is loaded in register r13, the address to be programmed is loaded in register r11/r12 (segment number in r11, segment offset in r12). ; sending of the programming command to the flash mov r5, #01554h ;load auxilary register r5 with command address ;(used in command cycle 1) mov r6, #02aa8h ;load auxilary register r6 with command address ;(used in command cycle 2) sxct dppo, #08h ;push data page pointer 0 and load it to point ;to segment 2 mov r7, #0a8h ;load register r7 with 1st ci enable command mov [r5], r7 ;command cycle 1 mov r13, #054h ;load register r7 with 2nd ci enable command mov [r6], r7 ;command cycle 2 mov r13, #0a0h ;load register r7 with program word command mov [r5], r7 ;command cycle 3 pop dpp0 ;restore dpp0: following addressing to the flash ;will use extended instructions ;r11 contains the segment to be programmed ;r12 contains the segment offset address to be programmed ;r13 contains the data to be programmed exts r11, #1 ;use extended addressing for next mov instruction mov [r12], r13 ;command cycle 4: the e/p.c. starts execution of ;programming command ; data_polling after word programming : data_polling : exts r11, #1 ;use extended addressing for next mov instruction mov r7, [r12] ;read flash status register (fsb) in r7 mov r6, r7 ;save it in r6 register ;check if fsb.7 = data.7 (i.e. r7.7 = r13.7) xor r7, r13 jnb r7.7, prog_ok ;check if fsb.5 = 1 (programming error) jnb r6.5, data_polling ;programming error: verify is flash programmed data is ok exts r11, #1 ;use extended addressing for next mov instruction mov r7, [r12] ;read flash status register (fsb) in r7 ;check if fsb.7 = data.7 xor r7, r13 jnb r7.7, prog_ok ;programming failed: flash remains in write operation. ;to go back to normal read operations, a read/reset ;command must be performed
AN1496 - application note 9/17 prog_error: mov r7, #0f0h ;load register r7 with read/reset command exts r11, #1 ;use extended addressing for next mov instruction mov r12], r7 ;address is dont care for read/reset command ... ;here place specific error handling code ... ... ;when programming operation finshed succesfully, flash is set ;back automatically to normal read mode prog_ok: .... .... 2.5 - erasing command example : performing the block erase command we assume that in the initialization phase the lowest 32 kbyte of flash memory (sector 0) have been mapped to segment 1. the registers r11/r12 contain an address related to the block to be erased (segment number in r11, segment offset in r12, eg; r11 = 01h, r12= 4000h will erase the block 1 - first 8 kbyte block). ; sending of the erasing command to the flash mov r5, #01554h ;load auxilary register r5 with command address ;(used in command cycle 1) mov r6, #02aa8h ;load auxilary register r6 with command address ;(used in command cycle 2) sxct dppo, #08h ;push data page pointer 0 and load it to point ;to segment 2 mov r7, #0a8h ;load register r7 with 1st ci enable command mov [r5], r7 ;command cycle 1 mov r13, #054h ;load register r7 with 2nd ci enable command mov [r6], r7 ;command cycle 2 mov r13, #080h ;load register r7 with block erase command mov [r5], r7 ;command cycle 3 mov r7, #0a8h ;load register r7 with 1st ci enable command mov [r5], r7 ;command cycle 4 mov r13, #054h ;load register r7 with 2nd ci enable command mov [r6], r7 ;command cycle 5 pop dpp0 ;restore dpp0: following addressing to the flash ;will use extended instructions ;r11 contains the segment of the block to be erased ;r12 contains the segment offset address of the block mov r7, #030h ;load register r7 with erase confirm code exts r11, #1 ;use extended addressing for next mov instruction mov [r12], r7 ;command cycle 6: the e/p.c. starts execution of ;erasing command after 96us time-out delay ;additional block commands may be sent here before the ;96us time-out expires.
AN1496 - application note 10/17 ; erase polling during block erase erase_polling: exts r11, #1 ;use extended addressing for next mov instruction mov r7, [r12] ;read flash status register (fsb) in r7 ;check if fsb.7 = 1 (i.e. r7.7 = 1) jb r7.7, erase_ok ;check if fsb.5 = 1 (erasing error) jnb r7.5, erase_polling ;programming failed: flash remains in write operation. ;to go back to normal read operations, a read/reset ;command must be performed erase_error: mov r7, #0f0h ;load register r7 with read/reset command exts r11, #1 ;use extended addressing for next mov instruction mov [r12], r7 ;address is dont care for read/reset command ... ;here place specific error handling code ... ... ;when erasing operation finshed succesfully, flash is ;set back automatically to normal read mode erase_ok: .... .... 2.6 - flash protection commands 2.6.1 - block protection block protection allows to protect flash internal blocks against inadvertent erasing and/or programming. for security reasons, once set, protection cannot be removed, even after erasing the flash. it can only be temporarily disabled using the "block temporary unprotection" command. 2.6.2 - code protection code protection allows to disable any read or jump to the st10 embedded flash from another memory (like internal ram, external memory). for security reasons, once set, code protection is permanent and cannot be cleared, even after erasing the flash. code protection can only be temporary disabled using the "code temporary unprotection" command. code temporary unprotection remains active until a code temporary protection command is executed or until reset (reset via the flash command interface, hardware, software, watchdog) 2.6.2.1 - using code protection with st10 when code protection is set, and when code may be executed from another memory before resuming code from on-chip-flash, the code protection should be disabled before calling the routine in the other memory. if not, a trap #00 illegal instruction will be generated when jumping back to the on-chip flash. 2.6.2.2 - code protection and bootstrap loader the code protection also applies in bootstrap mode : in st10 boostrap loader mode, it is not possible to read the flash or to jump into any address within the embedded flash.
AN1496 - application note 11/17 2.6.2.3 - code protection and block0 protection when code protection is set, it is still possible to erase and reprogram blocks that are not protected. as a consequence, if block0 is not protected, it would still be possible to erase block0 and reprogram it with a software to dump the remaining part of the flash. if block0 is protected when code protection is set, it is not possible to dump the flash content. example : performing the command read protection ;*************************************************************************** ***** ;read_block_protection ;input : none ;output: r0 contain the status of each block (if bit x is set, block x is protected) ;*************************************************************************** ***** read_block_protection proc near ; r0 = segment of flash push r1 ; r1 = first addr to write push r2 ; r2 = second addr to write push r3 ; r3 = data push r4 ; r3 = data push r5 ; r5 = pointer to data status movr0, dpp2:flash_seg mov r1, #even_comm ; retreive the even command addr mov r2, #odd_comm; retreive the odd command addr mov r3, #val1 exts r0, #1 mov[r1],r3; first write mov r3, #val2 exts r0, #1 mov[r2],r3; second write mov r3, #090h exts r0, #1 mov[r1],r3; third write mov r2,#8; r2 contain the number of block that remain to read mov r3,#0; r3 will contain the status mov r4,#1; r4 mask for status mov r1, r0 exts #monitor_seg,#1 movr5, #flash_status pop r5 ; r5 = pointer to data status pop r4 pop r3 pop r2 pop r1 ret read_block_protection endp
AN1496 - application note 12/17 2.7 - other flash commands example : performing the command read/reset we assume that in the initialization phase the lowest 32 kbyte of flash memory (sector 0) have been mapped to segment 1. according to the usual way of st10 data addressing with data page pointers, address bits a15 and a14 of a 16-bit command write address select the data page pointer (dpp) which contains the upper 10 bits for building the 24-bit physical data address. address bits a13...a0 represent the address offset. as the bits a14...a17 are dont care when written a flash command in the command interface (ci), we can choose the most conveniant dppx register for address handling. the following examples are making usage of dpp0. we just have to make sure, that dpp0 points to active flash memory space. to be independent of mapping of sector 0 we choose for all dpps which are used for flash address handling, to point to segment 2. for this reason we load dpp0 with value 08h (00 0000 1000b). mov r5, #01554h ;load auxilary register r5 with command address ;(used in command cycle 1) mov r6, #02aa8h ;load auxilary register r6 with command address ;(used in command cycle 2) scxt dppo, #08h ;push data page pointer 0 and load it to point ;to segment 2 mov r7, #0a8h ;load register r7 with 1st ci enable command mov [r5], r7 ;command cycle 1 mov r7, #054h ;load register r7 with 2cd ci enable command mov [r6], r7 ;command cycle 2 mov r7, #0f0h ;load register r7 with read/reset command mov [r5], r7 ;command cycle 3 . address is dont care pop dpp0 ;restore dpp0 value 2.8 - tips to reduce flash program and erase times 2.8.1 - reducing the programming time when block protection is enabled, block temporary unprotection commands shall be sent before erasing or programming command. as block unprotection remains active till the next reset, this means it is not necessary to repeat this command for each word to program. 2.8.2 - reducing erase times reducing erase time is simple with st10 0.35 m m embedded flash. several charge pumps are provided for each block, so erasing two blocks does not take twice as long as erasing one block (erasing 2 blocks still takes longer than erasing one block however). to benefit from the parallel erase, it is important to issue all the blocks you want with one block erase command. the chip erase command also erases the blocks in parallel. erasing a block of data erase commands perform two operations : first, they individually program each word to 0000h, then they use the tunnelling to set all bits to "1" at the same time. erasing time of a block can be reduced by more than 50% if all word are already programmed to 0000h. this specificity can be used in application where blocks of data are copied from 1 block to another and the old block is marked as "dirty". writting all data to 0000h of a "dirty" block will save time when erasing of this block will be performed.
AN1496 - application note 13/17 3 - embedded application aspects this chapter advises for embedded applications where the st10 embedded flash memory may be the only non volatile memory available. reading the flash while programming and field reprogramming are the 2 specific points raised by single chip embedded applications. 3.1 - reading the flash while erasing or programming during erasing or programming, the entire flash is not visible to the cpu, whatever the flash-block is erased or programmed. as a consequence on st10 software : C during erasing and programming, it is not possible to have access to the interrupt vector table and so all interrupts shall be disabled. C before erasing and programming, a small software loop shall be copied from the flash to the on-chip ram to run the minimum code needed to wait for the end of erasing or programming . C if code protection is activated, it should be temporary disabled before executing the code copied into the on-chip ram. there are 2 ways to deal with this constraint : one is minimizing the requirements in ram space used during erasing/programming and another one is maximizing the programming speed by duplicating all needed software into the on-chip ram. 3.1.1 - minimum software to be copied into the on-chip ram the minimum software to be copied into the on-chip ram is : C functions sending the erasing and or programming commands to the st10 embedded flash, C functions polling the flash status register for completion of the command and for error (see detailled specification). example of usage : this method can be implemented when it is necessary to program and/or erase some data in the st10 embedded flash during normal operation. 3.1.2 - maximizing programming performance at system level when the minimum software is copied into the on-chip ram, during erasing and/or programming, the cpu cannot run any other software (like communication) during that time. to maximize programming performance, user could handle the whole part or a part only of the communication handler. this requires : C that more software is copied into the on-chip ram, C the communication handler is not using interrupts, C the software loop polling the flash status register is modified to handle the communication process. example of usage : this method can be implemented when it is necessary to erase and program (re-program) the whole flash of the st10. 3.1.3 - suspend and resume commands as stand-alone flash memories, the 0.35 m m embedded flash controller features suspend and resume commands; this allows to suspend at any time the erasing or the programming process and resume it later on. once suspend command is completed, the st10 can access to a needed software routine (i.e. communication driver) which has not been relocated in the on-chip ram. example of usage : the error handler of the communication driver. note : the time for which the flash is not available is unchanged but this gives the possibility to suspend the process to run specific routines during flash erasing or programming (ex : communication protocol).
AN1496 - application note 14/17 3.2 - field reprogramming with st10f269 reprogramming in the field part or the whole application, requires to be able to deal safely with all the possible events that may occur in the field during the reprogramming of the flash. this analysis is application dependant and has to be carefully conducted by the user. this section assumes that users have experience with all the generic aspects of field reprogramming and will focus only on st10 specific events. 3.2.1 - reset whatever the possible causes of reset (spurious reset, external hardware reset, reset due to power-shut down), reset is one of the events possible during field reprogramming. as reset may occur during the erasing of the on-chip flash before it is re-programmed, st10 should be able to read a valid code from the flash at the next start-up. as a consequence, C block-0 (i.e. : starting at physical address : 000000h) should never be erased during field reprogram- ming. C block0 should contain all the routines to allow to restart the reprogramming routines (if those routines are in another block, this block also should never be erased). note : this restriction on block0 does not apply if st10 bootstrap loader mode is used for field reprogramming. (see code protection paragraph if code protection is used). flash bock write protection : it is recommanded to use the flash "set block protection" feature to protect the block(s) which contains all the needed software to restart the reprogramming routines. any inadvertent chip erase command will not affect those protected blocks. 3.2.2 - list of events and suggested handling methods 3.2.2.1 - supply out of st specification detection method : user should have specific hardware to detect whenever vcc comes out of st specification and generate a hardware reset as long this condition exist. suggested handling method : restart the whole reprogramming sequence at module level (i.e. : erasing + programing). 3.2.2.2 - st10 pll unlock as flash programming/erasing timings are not defined by the st10, pll unlock has no effect on the flash erasing and programming. usually, pll unlock will stop communication because of change in bit/ baud rate. detection method : not necessary (to be checked with application specific constraints). suggested handling method : restart the whole programming sequence (i.e. : at module level). 3.2.3 - generic aspects of flash field reprogramming this part is giving few advices for the field reprogramming. those advices are not specific to st10; they are generic to any embedded application that reprograms itself using a communication media with a programming station. the main points to control during flash reprogramming are : C completion of the reprogramming process itself, C events that may interrupt the reprogramming process.
AN1496 - application note 15/17 3.2.3.1 - completion of the reprogramming process the programming process is completed when the last word to be programmed has been programmed correctly (i.e. : status returned by the flash is ok). if, for any reason, the programming process is interrupted during the programming of the last word, the value written may be good at the next restart, but the retention time of this value may be limited. for this reason, it is recommanded that users consider the reprogramming to be "ok" only after the completion of the programming of the last word (ex : send an acknowledge to the programming station after the last word has been sucessfully programmed). evidence of completion of programming process : for traceability reasons, some users may want to record an evidence of the successfull completion of the reprogramming process. this can be done by programming a variable into the flash after the last valid word to be programmed. 3.2.3.2 - events that may interrupt the reprogramming process there may be other events that could interrupt the reprogramming process. the handling of those events, at module level and at st10 level, should be such that those events are detected as soon as possible and that the st10 will be able to restart the programming process. on st10 side, as st10 bank0 is never erased, it will be possible to restart the programming process (if we assume that all banks that have the code needed for reprogramming are never erased). restarting reprogramming : when interrupted, it is recommanded to restart the reprogramming process from the beginning (i.e. : erasing and programming).
AN1496 - application note 16/17 4 - quick summary this table gives a quick summary on st10 programming for 0.35 m m embedded flash : addressing : register indirect addressing needed for the commands to the embedded flash, programming language : can be high level (ex : c) except for the writting of the commands : must be in assembly to ensure register indirect addressing is used, polling the flash erase/program controller : preferred solution is via the flash status register. for increased software re-use for coming st10 variants, check that reserved bits are masked by software. code run from ram : the commands for erasing, programming and polling the completion of the commands should be run from the on-chip ram, interrupt disabled : no interrupt enabled during the execution of commands into the flash, code protection : once set, it is no more possible to dump the flash content from code in another memory (external flash, on-chip ram during bootstrap mode). for better protection, check that bock0 is erased protected. 5 - conclusion this application note has shown how easy it is to erase and program st10f269 and st10f280. it shows that st10 with 0.35 m m single voltage embedded flash memory are ideal for embedded applications where performance, security and reprogrammability are needed. 6 - applicatio n note v ersion inf ormation 6.1 - revision of 26th of february 2002 this is the first revis ion of the AN1496. 6.2 - revis ion of 25th of september 2013 updated disclaimer.
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